This invention relates to complementary field-effect transistor integrated circuit structures, and more particularly to a structure having an improved guardband configuration for greater protection from parasitic pnpn latchup.
Integrated circuits using complementary metal-oxide-semiconductor (CMOS) transistors are well known. Such circuits which combine both p- and n-channel enhancement mode transistors on the same substrate chip offer high performance, low standby power dissipation, high noise immunity and single power supply operation. Owing to these desirable characteristics, CMOS circuits are now widely used in a variety of applications such as random access memories and microprocessors. At present, CMOS circuits having extremely high packing density of devices on a single chip are being developed.
One problem with CMOS circuits is that parasitic active elements which are inherently a part of conventional CMOS structures can cause very large currents to flow between the power supply terminals of the circuit. In a conventional CMOS structure, p-channel devices are formed in the surface of an n-type bulk substrate wafer and n-channel devices are formed in the surface of a p-type tub region formed in the substrate. When a p-channel device and an n-channel device are placed in close proximity, the p-type source and drain regions of the p-channel device, the n-type bulk substrate region, the p-type bulk tub region and the n-type source and drain regions of the n-channel device form a pnpn structure which can operate as a silicon-controlled rectifier (SCR). This parasitic SCR can be triggered into a self-sustained high conductivity state known as the latchup state by noise signals of appropriate polarity and magnitude applied to the source or drain regions of the transistors. For example, latchup can be triggered by a noise transient pulse having a voltage whose magnitude exceeds that of the power supply voltage and which is picked up by an external terminal of the CMOS circuit. Once triggered, latchup of the parasitic SCR continues until the power supply voltages of the CMOS circuit are removed or are greatly reduced. The results of latchup are temporary malfunction of the CMOS circuit or, in some cases, permanent circuit damage.
Another characteristic of the latchup problem is that as the spacing between the p- and n-channel devices and the dimensions of the devices themselves are made smaller in order to achieve a higher circuit packing density, the parasitic SCR becomes more easily triggered. Consequently, as the packing density of a conventional CMOS circuit is increased, the circuit becomes more susceptible to latchup. Therefore, the latchup problem also imposes a limitation on the maximum packing density achievable with conventional CMOS structures.
A prior art solution to the latchup problem in CMOS circuits is to form relatively heavily doped p- and/or n-type annular regions called guardbands in the substrate and tub regions, respectively, and interposed between the p- and n-channel devices. The guardbands which are appropriately biased serve as collectors of minority carriers in their respective underlying regions to inhibit parasitic SCR action and raise the trigger threshold for latchup. The degree of latchup protection provided by the guardbands depends largely on their effectiveness in collecting minority carriers.
The prior art guardband structure consists of a p-type guardband in the n-type substrate surrounding the n-channel devices and/or an n-type guardband in the p-type tub region surrounding the n-channel devices. The prior art guardband structure is deficient in that the effectiveness of each guardband in collecting minority carriers can be diminished by the presence of transverse electric fields (i.e., electric fields having components parallel to the semiconductor surface) in the regions underlying the guardband. Inasmuch as transverse electric fields from a variety of origins such as voltage drops caused by junction leakage currents and capacitively coupled signal voltages are usually present in the bulk semiconductor regions of an operating CMOS circuit, the prior art guardband structure is hindered from being fully effective for collecting minority carriers. Owing to this deficiency, the prior art guardband configuration which is adequate for preventing latchup in CMOS circuits having the present packing density of devices becomes less adequate for the circuits having higher packing density that are currently being developed. Therefore, a need clearly exists for an improved guardband structure which is more effective for collecting minority carriers in the presence of a transverse electric field.